Current SLMs are used to monitor wafer production and enable wafer disposition. Thus, such SLMs are mandatory, but the goal is to minimize the area demand of these structures to allow the highest number of good chips per wafer during production. However, with the increasing complexity of modern products, more test structures are required, yet mechanical/physical limitations prevent any significant reduction in the size of the structures. Generally, needle cards cannot be manufactured with pitches significantly smaller than 72 micrometers (μm), for example, and the pad size cannot be reduced significantly below 35 μm×35 μm, for example.
The current industry standard for forming SLMs involves forming a single pad row with devices under test (DUTs) between probe pads, as illustrated in FIG. 1. In particular, a probe pad 101 and a DUT 103 are formed within a single probe pitch 105 of the pad row 107. Moreover, every pad row is touched sequentially to obtain the corresponding electrical results. Therefore, the maximum number of parametric test DUTs 103 is determined by the number of probe pads 101 in a single product scribe line, e.g., pad row 107. Also, the time required for testing is determined by the number of touchdowns.
A need therefore exists for a methodology enabling a reduction in the area demand for product monitoring structures without reducing the total number of DUTs and without introducing complicated new needle card probing processes, and the resulting device.